`timescale 10ns/1ps

module DFF_NegativeEdge_test;

	reg D, C, RESET;
	wire Q;
	
	
	DFF_NegativeEdge U0 (.*);

	initial
	begin
		C = 1'b0;
		forever #0.5 C=~C;
	end
	
	initial
	fork
		{D, RESET} <=2'b00;
		#3 D <= 1'b1;
		#5.2 RESET <=1'b1;
		#5.6 RESET <=1'b0;
	join
endmodule